ASIC Design
At the forefront of SoC design, our teams expertly navigate technologies spanning 0.25 µm to 5 nm. Our advanced techniques address critical aspects: DFT, power analysis, placement & routing, RC extraction, timing analysis, and IR drop/electromigration mitigation. All this, ensuring your project hits the market on time.
Expertise
RTL-to-GDSII, Netlist-to-GDSII, Spec-to-GDSII
Scan, ATPG, Memory BIST, Boundary Scan
ARM Processors / RISC-V CPU Configuration / Hardening
Digital IP hardening
Hard IP (GDSII) merge